High Speed VLSI Implementation of a Serial-in Parallel-Out Finite Field Multiplier
Abhinav V. Deshpande
*
School of Electronics Engineering (SENSE), Vellore Institute of Technology (VIT), Vellore, Tamil Nadu (T.N.), 632014, India.
*Author to whom correspondence should be addressed.
Abstract
A high-speed VLSI implementation of a 4-bit serial-in parallel-out finite field multiplier is presented. The presented design performs the multiplication by using a recorded normal basis, a permutation of a type II optimal normal basis. The multiplier was realized in a 0.18 µm CMOS technology by using multiplies of pseudo NMOS. The multiplier was simulated, and functioned correctly up to a clock rate of 0.5 GHz. Already it was implemented by using multiplies of the area as compared to the other CMOS logic structures. The architecture has a very regular structure which greatly simplifies the VLSI implementation by using the CMOS logic structures. The performance of the multiplier was examined by using Mentor graphics tool and the model parameters of a 0.18 µm CMOS process.
Keywords: Immunogenetics, Finite field arithmetic, H-Y and H-2 antibodies, recorded normal basis, sex ratio, serial-in parallel-out finite field multipliers, binary field multiplication, CMOS logic structures, CMOS technology